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may 2016 ? 201 4 fairchild semiconductor corporation www.fairchildsemi.com gf001 h ? rev. 1.1 gf001 h green - mode fairchild power switch (fps?) gf001 h green - mode fairchild power switch (fps ? ) features ? a dvanced b urst m ode o peration at n o - l oad c ondition ? 700 v high - voltage jfet startup circuit ? internal avalanche - rugged 700 v sensefet ? built - in 5 ms soft - start ? peak - current - mode control ? cycle - by - cycle current limiting ? leading - edge blanking (leb) ? synchronized slope compensation ? frequency modulation to attenuating emi ? internal overload / open - loop protection (olp) ? v dd under - voltage lockout (uvlo) ? v dd over - voltage protection (ovp) ? internal aut o - restart circuit (olp, v dd ovp) ? adjustable peak current limit description the GF001H is a next - generation, g reen - m ode fairchild power switch (fps ? ) . it integrates an advanced current - mode pulse w idth m odulator (pwm) and an avalanche - rugged 700 v sensefet in a single package , allowing auxiliary power designs with higher standby energy efficiency, reduced size, improved reliability, and lower sys tem cost than previous solutions. a new frequency modulation reduces emi emission and b uilt - in synchronized slope compensation allows stable peak - current - mode control over a wide range of input voltage. requiring a minimum number of external components, the gf001 h provides a solid platform for cost - effective flyback converter design with low standby power consumption. ordering information part number s ensefet operating temperature range package packing method GF001H n 2 a 700 v - 40 c to +10 5 c 8 - pin, dual inl ine package (dip) tube
? 201 4 fairchild semiconductor corporation www.fairchildsemi.com gf001 h ? rev. 1.1 2 gf001 h green - mode fairchild power switch (fps?) application diagram figure 1. typical flyback application output power table ( 1 ) product 230 v ac 15% ( 2 ) 85 - 265 v ac adapter ( 3 ) open - frame ( 4 ) adapter ( 3 ) open - frame ( 4 ) GF001H n 14 w 20 w 11 w 16 w notes: 1. the maximum output power can be limited by junction temperature . 2. 230 v ac or 100/115 v ac with voltage doublers . 3. typical continuous power in a non - ventilated enclosed adapter , with sufficient drain pattern of printed circuit board (pcb) as a heat sink, at 50 c ambient . 4. maximum practical continuous power in an open - frame , design with sufficient drain pattern of printed circuit board (pcb) as a heat sink, at 50 c ambient . block diagram figure 2. internal b lock diagram l n e m i f i l t e r + + h v v d d + g n d f b i p k d r a i n p w m + f b g n d v d d i p k 4 h v s t a r t - u p 5 . 4 v s o f t d r i v e r q s r 1 2 v / 6 v u v l o g r e e n m o d e o l p o v p d e l a y d e b o u n c e v d d - o v p 2 5 6 , 7 , 8 3 1 4 . 6 v h v l i n e v o l t a g e s a m p l e c i r c u i t b r o w n o u t p r o t e c t i o n o l p 3 r o l p c o m p a r a t o r p w m c o m p a r a t o r i n t e r n a l b i a s s o f t - s t a r t v l i m i t s l o p e c o m p e n s a t i o n r c u r r e n t l i m i t c o m p a r a t o r s o f t - s t a r t c o m p a r a t o r o l p d r a i n i p k v l i m i t s / h 3 . 5 v o v p 5 0 a z f b o s c i l l a t o r w i t h e m i a t t e n u a t o r r e - s t a r t p r o t e c t i o n m a x . d u t y v p w m v p w m o t p
? 201 4 fairchild semiconductor corporation www.fairchildsemi.com gf001 h ? rev. 1.1 3 gf001 h green - mode fairchild power switch (fps?) confidential and pro prietary do not distribute marking information figure 3. top mark pin configuration figure 4. pin assignment pin definitions pin # name description 1 gnd ground . this pin internally connects to the sensefet source and signal ground of the pwm controller. 2 vdd supply v oltage of the ic . typically the hold - up capacitor connects from this pin to ground. a r ectifier diode in series with the transformer auxiliary winding connects to this pin to supply bias during normal operation. 3 fb feedback . the signal from the external compensation circuit connects to this pin. the pwm duty cycle is determined by comparing the signal on this pin and the internal current - sense signal. 4 ipk adjust p eak c urrent . typically a resistor connects from this pin to the gnd pin to program the current - limit level. the internal current source (50 a) introduces voltage drop across the resisto r, which determines the current - limit level of pulse - by - pulse current limit. 5 hv startup . typically , resistors in serious from d c line connect to this pin to supply internal bias and to charge the external capacitor connected between the vdd pin and the gnd pin during startup. this pin is also used to sense the line voltage for brownout protection . 6 drain sensefet d rain . this pin is designed to directly drive the transformer. 7 8 f C fairchild l ogo z C plant c ode x C 1 - d igit y ear c ode y C 1 - d igit w eek c ode tt C 2 - digit d ie r un c ode t C package t ype (n: dip) m C m anufacture f low c ode 8 1 z x y t t g f 0 0 1 h t m 8 7 6 5 1 2 3 4 g n d v d d f b i p k h v d r a i n d r a i n d r a i n
? 201 4 fairchild semiconductor corporation www.fairchildsemi.com gf001 h ? rev. 1.1 4 gf001 h green - mode fairchild power switch (fps?) absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stres ses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v drain drain pin voltage ( 5 , 6 ) 700 v i dm drain current pulsed ( 7 ) 8 .0 a e as single pulsed avalanche energy ( 8 ) 140 mj v dd dc supply voltage 25 v v fb fb pin input voltage - 0.3 6 .0 v v ipk ipk pin input voltage - 0.3 6 .0 v v hv hv pin input voltage 7 00 v p d power dissipation (t a j operating junction temperature - 40 internally limited ( 9 ) ? stg storage temperature range - 55 +150 ? l lead soldering temperature (wave soldering or ir, 10 seconds) +260 ? notes : 5. all voltage values, except differential voltages, are given with respect to the network ground terminal. 6. stresses beyond those listed under a bsolute m aximum r atings may cause permanent damage to the device. 7. non - repetitive rating: p ulse width is limited by the maximum junction temperature. 8. l = 51 mh, starting t j = 25 c . 9. internally limited by over - temperature protection(otp). refer to t otp . thermal resistance table symbol parameter value unit ja junction - to - air t hermal resistance 86 ? c/w jt junction - to - package t hermal resistance ( 10 ) 20 ? c/w note : 10. measured on the package top surface. esd capability symbol parameter value unit esd human body model, jesd22 - a114 ( 11 ) all pins excluding hv pin 7 kv all pins including hv pin 3 charged device model, jesd22 - c101 ( 11 ) all pins excluding hv pin 2 all pins including hv pin 2 note : 11. meets jedec standards jesd 22 - a114 and jesd 22 - c101.
? 201 4 fairchild semiconductor corporation www.fairchildsemi.com gf001 h ? rev. 1.1 5 gf001 h green - mode fairchild power switch (fps?) electrical characteristics v dd =15 v, and t a =25 c unless otherwise specified. symbol parameter condition min. typ. max. unit sensefet section ( 12 ) bv dss drain - source breakdown voltage v ds = 700 v, v gs = 0 v 700 v i dss zero - gate - voltage drain current v ds = 700 v, v gs = 0 v 50 ds = 560 v, v gs = 0 v, t c = 125 c 200 r ds(on) drain - source on - state resistance ( 12 ) v gs = 10 v, i d = 0.5 a 6.0 7.2 iss input capacitance v gs = 0v , v ds = 25 v, f = 1 mhz 550 715 pf c oss output capacitance v gs = 0 v, v ds = 25 v, f = 1 mhz 38 50 pf c rss reverse transfer capacitance v gs = 0 v, v ds = 25 v, f = 1 mhz 17 26 pf t d(on) turn - on delay v ds = 350 v, i d = 1.0 a 20 50 ns t r rise time v ds = 350 v, i d = 1.0 a 15 40 ns t d(off) turn - off delay v ds = 350 v, i d = 1.0 a 55 120 ns t f fall time v ds = 350 v, i d = 1.0 a 25 60 ns control section vdd section v dd - on uvlo start threshold voltage 11 12 1 3 v v dd - off 1 uvlo stop threshold voltage 5 6 7 v v dd - off2 i dd - olp enable threshold voltage 8 9 10 v v dd - olp v dd v oltage threshold for hv startup turn - on at protection mode 5 6 7 v i dd - st startup supply current v dd - on C dd - op1 operating supply current with normal switching o peration v dd =15 v, v fb =3 v 3.8 ma i dd - op2 operating supply current without switching operation v dd =15 v, v fb =1 v 1.8 ma i dd - olp internal s ink ing current v dd - olp + 0.1 v 30 6 0 90 a v d d - ovp v dd over - voltage protection 23 24 25 v t d - vdd ovp v dd over - voltage protection debounce time 40 105 170 s hv section i hv supply current drawn from hv pin hv=120 v dc , v dd =0 v with 10 f 1.5 5.0 ma v hv minimum hv voltage for v dd being charged to v dd - on r hv =0 a = - 40 c to 105 c 30 v i hv - lc leakage current after start up hv=700 v, v dd =v dd - off1 +1 v 10 a v d c - on brown - in t hreshold level (v dc ) dc voltage applied to hv pin through 200 k d c - off brownout t hreshold level (v dc ) 89 99 109 v t uvp brownout protection time 0.8 1.2 1.6 s continued on the following page
? 201 4 fairchild semiconductor corporation www.fairchildsemi.com gf001 h ? rev. 1.1 6 gf001 h green - mode fairchild power switch (fps?) electrical characteristics (continued) v dd =15 v, t a =25 c unless otherwise specified. symbol parameter condition min. typ. max. unit oscillator section f osc frequency in nominal mode center frequency 94 100 106 khz f m frequency modulation 6 khz f osc - g green - mode frequency 20 23 26 khz f dv frequency variation vs. v dd deviation v dd = 11 v to 22 v 5 % f dt frequency variation vs. temperature deviation ( 12 ) t a = - 40 c to 105 c 5 % feedback input section a v internal voltage dividing factor of fb pin ( 1 2 ) 1/4.5 1/4.0 1/3.5 v/v z fb pull - up impedance of fb pin 15 21 27 k fb - open fb pin pull - up voltage fb pin open 5.2 5.4 5.6 v v fb - olp fb voltage threshold to trigger open - loop protection 4.3 4.6 4.9 v t d - olp delay of fb pin open - l oop protection 46 56 66 ms v fb - n fb voltage threshold to exit green mode v fb is rising 2.4 2.6 2.8 v v fb - g fb voltage threshold to e nter green mode v fb is falling v fb - n - 0.2 v v fb - zdc fb voltage threshold to enter zero - duty state v fb is falling 1. 1 1.2 1. 3 v v fb - zdcr fb voltage threshold to exit zero - duty state v fb is rising v fb - zdc +0.1 v ipk pin section v ipk - open ipk pin open voltage 3.0 3.5 4.0 v v ipk - h internal upper clamping voltage of ipk pin ( 12 ) 3 v v ipk - l internal lower clamping voltage of ipk pin ( 12 ) 1.5 v i pk internal current source of ipk pin t a = - 40 c to 105 c , v ipk =2.25 v 45 50 55 a i lmt - h flat threshold level of current limit for the highest ipk level v ipk =3 v 0.90 1.00 1.10 a i lmt - l flat threshold level of current limit for the lowest ipk level v ipk =1.5 v 0.45 0.50 0.55 a current - sense section ( 13 ) t pd current limit turn - off delay ( 14 ) 100 200 ns t leb leading - edge blanking time ( 14 ) 160 210 260 ns t s s soft - start t ime ( 12 ) 5 ms gate section ( 13 ) dcy max maximum duty cycle 70 % over temperature protection section (otp) t otp junction temperature to trigger otp ( 12 ) 140 c notes: 12. guaranteed by design; not 100% tested in production. 13. pulse test: pulse width 300 s, duty 2%. 14. these parameters, although guaranteed, are tested in wafer - sort process .
? 201 4 fairchild semiconductor corporation www.fairchildsemi.com gf001 h ? rev. 1.1 7 gf001 h green - mode fairchild power switch (fps?) typical characteristics figure 5. v d d - on vs. temperature figure 6. v dd - off1 vs. temperature figure 7. v dd - off2 vs. temperature figure 8. v dd - ovp vs. temperature figure 9. v dd - o l p vs. temperature figure 10. i dd - op1 vs. temperature figure 11. v d c - on vs. temperature figure 12. v d c - off vs. temperature
? 201 4 fairchild semiconductor corporation www.fairchildsemi.com gf001 h ? rev. 1.1 8 gf001 h green - mode fairchild power switch (fps?) typical characteristics (continued) figure 13. v fb - open vs. temperature figure 14. v fb - olp vs. temperature figure 15. z fb vs. temperature figure 16. i pk vs. temperature figure 17. f osc vs. temperature figure 18. f osc - g vs. temperature
? 201 4 fairchild semiconductor corporation www.fairchildsemi.com gf001 h ? rev. 1.1 9 gf001 h green - mode fairchild power switch (fps?) functional description startup operation the hv pin is typically connected to the dc link input through one resistor (r hv ), as shown in figure 19 . when the dc input voltage is applied, the v dd hold - up capacitor is charged by the line voltage through the resistor. after v dd voltage reaches the turn - on threshold voltage (v dd - on ), the sta rtup circuit charging the v dd capacitor is switched off and v dd is supplied by the auxiliary winding of the transformer. once the GF001H starts, it continues operation until v dd drops below 6 v (v dd - off1 ). th e ic startup time with a given d c input voltage is: t c ln c c - - ( 1 ) figure 19. startup circuit brown - in/out function the hv pin can detect th e dc link voltage using a switched voltage divider that consists of external resistor (r hv ) and internal resistor (r ls ) , as shown in figure 19 . the internal dc input voltage sensing circuit detects the input voltage using a sampling circuit and peak - detection circuit . since the voltage divider causes power consumption when it is swi tched on, the switching is driven by a signal with a very narrow pulse width to minimize power loss. the sampling frequency is adaptively changed according to the load condition to minimize power consumption in light - load condition. based on the detected dc input voltage, brown - in and brownout thresholds are determined. since the internal resistor (r ls ) of the voltage divider is much smaller than r hv , the thresholds are g iven : ( 2 ) ( 3 ) pwm control the GF001H employs current - mode control, as shown in figure 20 . an opto - coupler (such as the h11a817a) and shunt regulator (such as the ka431) are typically used to implement the feedback network. comparing the feedback voltage with the voltage across th e r sense resistor makes it possible to control the switching duty cycle. a synchronized positive slope is added to the sensefet current information to guarantee stable current - mode control over a wide range of input voltage. the built - in slope compensation stabilizes the current loop and prevents sub - harmonic oscillation. figure 20. current mode control soft - start the GF001H has an interna l soft - start circuit that progressively increases the pulse - by - pulse current limit level of mosfet during startup to establish the correct working conditions for transformers and capacitors, as shown in figure 21 . the current limit levels have nine steps, as shown in figure 22 . this prevents transformer saturation and reduces stress on the secondary diode during startup. figure 21. soft - start and current - limit circuit a c l i n e n a c d d h v v d d g f 0 0 1 h r h v 2 5 + - 1 2 / 6 v l i n e s e n s i n g v d d g o o d e m i f i l t e r r l s d c l i n k 3 o s c 5 . 4 v r 3 r g a t e d r i v e r k a 4 3 1 z f 6 d r a i n 7 8 p w m c o m p a r a t o r v o s l o p e c o m p e n s a t i o n + + f b p r i m a r y - s i d e s e c o n d a r y - s i d e r s e n s e 3 o s c 5 . 4 v r 3 r g a t e d r i v e r z f 6 d r a i n 7 8 p w m c o m p a r a t o r s l o p e c o m p e n s a t i o n + + f b r s e n s e v l m t v s s c u r r e n t l i m i t c o m p a r a t o r s s c o m p a r a t o r
? 201 4 fairchild semiconductor corporation www.fairchildsemi.com gf001 h ? rev. 1.1 10 gf001 h green - mode fairchild power switch (fps?) figure 22. current limit variation during soft - start adjustable peak current limit the peak current limit is programmable using a resistor on the ipk pin. the internal current 50 a source for the ipk pin generates voltage drop across the resistor. the voltage of the ipk pin determines the current - limit level. since the upper and lower clamping voltage of the ipk pin are 3 v and 1.5 v, respectively; the suggested resistor value is from 30 k to 60 k. green mode as output load condition is reduced, the switching loss becomes the largest power loss factor. GF001H uses the fb pin voltage to monitor output load condition. as output load decreases, v fb decreases and switching frequency declines, show in figure 23 . once v fb falls to 2.4 v, the switching frequency varies between 21.5 khz and 24.5 khz before b urst m ode operation. at burst m ode operation, random frequency fluct uat ion still functions. as v fb falls below v fb - zdc , the GF001H enters burst mode, where pwm switching is disabled. the output voltage starts to drop, causing the feedback voltage to rise. once v fb rises above v fb - zdc r , switching resumes. burst mode alternately enables and disables sw itching, thereby reducing switching loss to reduce power consumption, shown in figure 24 . figure 23. pwm frequency figure 24. burst - mode operation protections the GF001H provides protection function s that include over l oad / open - loop protection (olp) and over - voltage protection (ovp) . all the protections are implemented as a uto - r estart m ode. once the f ault condition is detected, switching is terminated and the sensefet remains off, t his causes v dd to fall. when v dd falls to 6 v , the protection is reset and hv startup circuit charges v dd up to 12 v voltage, allowing restart . open - loop / overload protect ion ( olp ) because of the pulse - by - pulse current - limit capability, the maximum peak current through the sensefet is limited and maximum input power is limited. if the output consumes more than th e limited maximum power, the output voltage (v o ) drops below the set voltage. the current through the opto - coupler led and the transistor become virtually zero and fb voltage is pulled high , shown in figure 25 . if feedback vo ltage is above 4.6 v for longer than 56 ms, olp is triggered. this protection is also triggered when the feedback loop is open due to a soldering defect . figure 25. olp operation v dd over - voltage protection (ovp) if the secondary - side fee dback circuit malfunctions or a solder defect causes an opening in the feedback path, the current through the opto - coupler transistor becomes virtually zero. f eedback voltage climbs in a similar manner to the overload situation, forcing the preset maximum current to be supplied to the smps until the overload protection triggers. since more energy than required is provided to the output, the output voltage may exceed the rated voltage before the overload protection triggers, resulting in the breakdown of the devices in the secondary side. to prevent this situation, an ovp circuit is employed. since v dd voltage is proportional to the output voltage by the trans former coupling, the over - voltage of output is indirectly detected using v dd voltage. the ovp is triggered when v dd voltage reaches 24 v . debounce time (typically 1 05 s) is applied to prevent false trigger ing by switching noise. two - l evel uvlo since all the protections of the GF001H are auto - restart, the power supply repeats shutdo wn and restart until the fault condition is removed. GF001H has two - level uvlo , which is enabled when protection is triggered , to delay the re - startup by slowing down the discharge of v dd . this effectively reduces the input power of the power supply during the fault condition , minimizing the voltage/current stress of the switching devices. figure 26 shows the normal uvlo operation and two - step uvlo o peration. when v dd drops to 6 v without triggering the protection, pwm st ops switching and v dd 0 . 6 4 m s 0 . 4 5 i l m t 0 . 5 2 i l m t 0 . 5 9 i l m t 0 . 6 6 i l m t 0 . 7 3 i l m t 0 . 8 0 i l m t 0 . 8 6 i l m t 0 . 9 3 i l m t i l m t 1 . 9 2 m s 3 . 2 2 m s 4 . 5 0 m s 1 . 2 8 m s 2 . 5 6 m s 3 . 8 6 m s 5 . 1 2 m s v f b p w m f r e q u e n c y v f b - z d c v f b - z d c r v f b - g v f b - n 1 0 6 k h z 2 4 . 5 k h z r a n d o m f r e q u e n c y m o d u l a t i o n r a n g e 9 4 k h z 2 1 . 5 k h z v f b i d r a i n v o s w i t c h i n g d i s a b l e d v f b . z d c s w i t c h i n g d i s a b l e d v f b . z d c r 5 . 4 v v f b - o l p o l p s h u t d o w n d e l a y o l p t r i g g e r e d v f b ( 4 . 6 v ) 5 6 m s
? 201 4 fairchild semiconductor corporation www.fairchildsemi.com gf001 h ? rev. 1.1 11 gf001 h green - mode fairchild power switch (fps?) is charged up by the hv startup circuit. meanwhile, when the protection is triggered, GF001H has a different v dd discharge profile. once the protection is triggered, the ic stops switching and v dd drops. when v dd drops to 9 v, the operating current becomes very small and v dd is slowly discharged. when v dd is naturally discharged down to 6 v, the protection is reset and v dd is charged up by the hv startup circuit. once v dd reaches 12 v, the ic resumes switching operation. figure 26. two - level uvlo v d d - o n v d s v d d - o f f 2 v d d - o l p 1 2 v 9 v 6 v i d d - o p 1 n o r m a l u v l o w i t h o u t p r o t e c t i o n ( e x . a u x w i n d i n g d i s c o n n e c t e d ) i d d - o l p i d d - s t l i n e i s c o n n e c t e d v d d - o n v d s v d d - o f f 2 v d d - o l p 1 2 v 9 v 6 v p r o t e c t i o n t r i g g e r s i d d - o p 1 i d d - o l p i d d - s t l i n e i s c o n n e c t e d
8 5 4 1 notes: a) this package conforms to jedec ms-001 variation ba which defines b) controling dims are in inches c) dimension s are exclusive of burrs, mold flash, and tie bar extrusions. d) dimension s and tolerances per asme y14.5m-2009 e) drawing filename and revsion: mkt-n08mrev2. 0.400 0.355 [ 10.160 9.017 ] 0.280 0.240 [ 7.112 6.096 ] 0.195 0.115 [ 4.965 2.933 ] min 0.015 [0.381] max 0.210 [5.334] 0.100 [2.540] 0.070 0.045 [ 1.778 1.143 ] 0.022 0.014 [ 0.562 0.358 ] 0.150 0.115 [ 3.811 2.922 ] c 0.015 [0.389] gage plane 0.325 0.300 [ 8.263 7.628 ] 0.300 [7.618] 0.430 [10.922] max (0.031 [0.786]) 4x 4x for 1/2 lead style full lead style 4x half lead style 4x 0.10 c seating plane pin 1 indicator 0.031 [0.786] min 0.010 [0.252] min 8x for full lead style 2 versions of the package terminal style which are shown here.
www. onsemi.com 1 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 www.onsemi.com literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ? semiconductor components industries, llc

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